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16.5.4 USARTn_CMD - Command Register
Offset
0x00C
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:12
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
11
CLEARRX
0
W1
Clear RX
Set to clear receive buffer and the RX shift register.
10
CLEARTX
0
W1
Clear TX
Set to clear transmit buffer and the TX shift register.
9
TXTRIDIS
0
W1
Transmitter Tristate Disable
Disables tristating of the transmitter output.
8
TXTRIEN
0
W1
Transmitter Tristate Enable
Tristates the transmitter output.
7
RXBLOCKDIS
0
W1
Receiver Block Disable
Set to clear RXBLOCK, resulting in all incoming frames being loaded into the receive buffer.
6
RXBLOCKEN
0
W1
Receiver Block Enable
Set to set RXBLOCK, resulting in all incoming frames being discarded.
5
MASTERDIS
0
W1
Master Disable
Set to disable master mode, clearing the MASTER status bit and putting the USART in slave mode.
4
MASTEREN
0
W1
Master Enable
Set to enable master mode, setting the MASTER status bit. Master mode should not be enabled while TXENS is set to 1. To enable
both master and TX mode, write MASTEREN before TXEN, or enable them both in the same write operation.
3
TXDIS
0
W1
Transmitter Disable
Set to disable transmission.
2
TXEN
0
W1
Transmitter Enable
Set to enable data transmission.
1
RXDIS
0
W1
Receiver Disable
Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded.
0
RXEN
0
W1
Receiver Enable
Set to activate data reception on U(S)n_RX.
2011-04-12 - d0001_Rev1.10
204
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